University of California, Santa Cruz, Class of 2017

B.S. in Computer Engineering with a focus in Digital Hardware

Classes

CE 153: Digital Signal Processing CE 129: Senior Design Project CE 122: VLSI Digital System Design CE 121: Microprocessor Design CE 185: Technical Writing EE 103: Signals and Systems EE 171: Analog Circuit Design

CE 125: Logic Design with Verilog EE 101: Intro to Circuits CS 101: Algorithms and Abstract Data Types CS 12B: Data Structures CE 100: Logic Design CE 110: Computer Architecture CE 13: Computer Systems and C Programming CE 12: Computer Systems and Assembly Language

Class Projects

• CE 129: Senior Design Project

  Interdisciplinary and corporate sponsored senior design project that maintained a professional relationship with Plantronics Inc. Tasked to create a prototype replacement for Plantronics' outdated audio test equipment. Designed LabVIEW software for the NI cRIO microcontroller. Utilized event driven, object oriented, and multithreaded LabVIEW techniques for robust and easily modifiable software architecture. Engineered DSP algorithms for crest factor optimization, calibration, and audio signal generation and analysis. Desined a triggering method for capturing a response audio waveform. Utilized DMAs and FIFO buffers for communicating between the RTOS and FPGA modules. Project was sucessful and we were able to deliver a working prototype replacement tester.

• CE 185: Technical Writing

  Research Paper: The History and Modern Application of the Vacuum Tube Transistor. View PDF

  Oral Presentation: Room Acoustics. View PDF

  Poster Presentation: Home Theater Room Treatment. View PDF

• EE 171: Analog Circuits

  Using a single BJT (2N3904) transistor, I designed an amplifier that satisfied 10V/V gain and 20Hz-20KHz minimum bandwidth constraints under a 10KOhm load resistance. My design included blocking capacitors, proper biasing, and emitter degeneration.

• CE 125: Logic Design with Verilog

  Using verilog, I designed a processor that implemented Fetch (Instruction Cache) , Decode (Registry File, Sign Extend) , and Execute (ALU). This design implemented the multi-stage pipeline using fluid flops. Used GTKWave and C++ testbenches for debugging.

• CE 100: Logic Design

  Created a fly catcher game using an FPGA interfacing with a computer monitor via VGA. I used Xilinx ISE to program the FPGA board. Updated display with graphics and controlled the fly capture mechanism using the buttons on the FPGA board. Involved many finite state machines in order to control game logic.

Academic Work Experience

• Leep Lab Research Internship (December 2015 - December 2016)

  Worked under Professor Kristian Vargas Lopez on a behavioral economics project. My job was to create a facial recognition program that captured and logged the emotional state of each test subject. This was done in Linux using C++ with Affdex SDK, OpenCV, and Boost. I also worked with Shimmer sensors to capture and log the heart rate (PPG) and skin conductance (GSR) of the test subjects.

• Database Systems II Grader/Tutor (April 2017 - June 2017)

  Graded C++ programming assignments and tutored students for Sheldon Finkelstein’s Database Systems II computer science capstone course. Tested student's implementation of a record based database system using C++ testbenches. Assisted students regarding C++ and course concepts.